Probabilistic Error Propagation Modeling in Logic Circuits
- Citation:
- Gupta S, Van Gemund AJC, Abreu R. 2011. Probabilistic Error Propagation Modeling in Logic Circuits. IEEE Fourth International Conference on Software Testing, Verification and Validation Workshops - ICSTW. :617–623.
Date Presented:
MarchAbstract:
Recent study has shown that accurate knowledge of the false negative rate (FNR) of tests can significantly improve the diagnostic accuracy of spectrum-based fault localization. To understand the principles behind FNR modeling in this paper we study three error propagation probability (EPP) modeling approaches applied to a number of logic circuits from the 74XXX/ISCAS-85 benchmark suite. Monte Carlo simulations for random injected faults show that a deterministic approach that models gate behavior provides high accuracy (O(1%)), while probabilistic approaches that abstract from gate modeling generate higher prediction errors (O(10%)), which increase with the number of injected faults.
Citation Key:
gupta2011probabilisticDOI:
10.1109/ICSTW.2011.40
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