%0 Conference Paper
%B IEEE Fourth International Conference on Software Testing, Verification and Validation Workshops - ICSTW
%D 2011
%T Probabilistic Error Propagation Modeling in Logic Circuits
%A Gupta, Shekhar
%A Van Gemund, Arjan JC
%A Rui Abreu
%C Berlin, Germany.
%I IEEE
%P 617–623
%X <p>Recent study has shown that accurate knowledge of the false negative rate (FNR) of tests can significantly improve the diagnostic accuracy of spectrum-based fault localization. To understand the principles behind FNR modeling in this paper we study three error propagation probability (EPP) modeling approaches applied to a number of logic circuits from the 74XXX/ISCAS-85 benchmark suite. Monte Carlo simulations for random injected faults show that a deterministic approach that models gate behavior provides high accuracy (O(1%)), while probabilistic approaches that abstract from gate modeling generate higher prediction errors (O(10%)), which increase with the number of injected faults.</p>
%8 March
%> https://haslab.uminho.pt/sites/default/files/ruimaranhao/files/tebug2011_submission_6.pdf