FINAL
RESULT |
Paper ID |
Authors |
Affiliation |
Title |
distinguished
paper |
p23 |
C. Mannino, H. Rabah, C.
Tanougast, Y. Berviller, M. Janiaut and S. Weber |
Laboratoire d'Instrumentation
Electronique de Nancy (L.I.E.N.), France |
OPTIMIZED FPGA IMPLEMENTATION OF
A MULTI PROGRAM PCR MEASURMENT SYSTEM IN DVB-T |
distinguished
paper |
p10 |
Vassiliadis D. Nikolaos, N.
Kavvadias, G. Theodoridis, S. Nikolaidis |
Aristotle University of
Thessaloniki, Greece |
A RISC ARCHITECTURE EXTENDED BY
AN EFFICIENT TIGHTLY COUPLED RECONFIGURABLE UNIT |
distinguished
paper |
p17 |
Chris Clark, Craig Ulmer |
Georgia Tech, Sandia National
Labs, USA |
NETWORK INTRUSION DETECTION
SYSTEMS ON FPGAS WITH ON-CHIP NETWORK INTERFACES |
distinguished
paper |
p5 |
T. Kerins, W. P. Marnane,
E. M. Popovici, |
University College Cork, Ireland |
An FPGA Implementation of a
Flexible Secure Elliptic Curve Cryptography Processor |
distinguished
paper |
p32 |
Minoru Watanabe and Fuminori
Kobayashi |
Kyushu Institute of Technology
in Japan, Minoru Watanabe |
A dynamic optically
reconfigurable gate array using dynamic method |
distinguished
paper |
p9 |
Vanderlei Bonato, Márcio M.
Fernandes, Eduardo Marques |
University of São Paulo, Brasil |
A FAULT TOLERANT GESTURE
RECOGNITION SYSTEM FOR MOBILE ROBOT |
regular
paper |
p15 |
Rui Rodrigues, João Cardoso |
Univ. of Algarve, Portugal |
Pipelining Sequences of Loops: A
First Example |
regular
paper |
p14 |
Peter Mårtensson, Jans Persson,
Shang Xue, Bengt Oelmann |
Mid Sweden University, Sweden |
Efficient Decoding of
Variable-Length Encoded Image Data on the Nios II Soft-Core Processor |
regular
paper |
p18 |
T. Liu, C. Tanougast, P. Brunet,
Y. Berviller, H. rabah and S. Weber |
Université Henri Poincaré Nancy
I, France |
Optimise FPGA Implementation of
an AES Algorithm for Embedded Application |
regular
paper |
p4 |
Masahiro
IIDA, Shinya ABE, Hisashi TSUKIASHI, Ryoji OGATA, and Toshinori SUEYOSHI |
Kumamoto University, Japan |
Adopting the Small-World Network
in Routing Structure of FPGA |
regular
paper |
p1 |
Rui Rodrigues, João Cardoso |
Univ. of Algarve, Portugal |
A TEST INFRASTRUCTURE FOR
COMPILERS TARGETING FPGAS |
regular
paper |
p27 |
Pedro O. Domingos, Horácio C.
Neto |
IST, Portugal |
AN EFICIENT, LOW RESOURCE,
ARCHITECTURE FOR BACKPROPAGATION NEURAL NETWORKS |
regular
paper |
p16 |
Aparna
Nagargadde, Sridhar Gangadharpalli, and Sridhar V. |
Applied Research Group, Satyam
Computer Services Limited |
A Methodology for Parameterized
Algorithm Design to Support Flexible FPGA Based System Design |
regular
paper |
p11 |
Thomas Reinemann, Roland
Kasper |
University Magdeburg, Germany |
FUNCTION REPLACEMENT OF HARD
REAL-TIME SYSTEMS USING PARTIAL RECONFIGURATION |
regular
paper |
p26 |
Dong Kwan Kim, Cameron
Patterson, and Peter Athanas |
Virginia Polytechnic Institute
and State University, USA |
Open Architecture Hierarchical
Placement for FPGA Datapath Designs |
regular
paper |
p28 |
Katarina Paulsson, Michael
Hübner, Hong Zou, Jürgen Becker |
Universitaet Karlsruhe (TH),
Germany |
Realisation of Real-Time Control
Flow Oriented Automotive Applications on a Soft-core Multiprocessor System
based on Xilinx Virtex II FPGAs |
regular
paper |
p20 |
Germán León, José M. Claver
and Germán Fabregat |
University Jaume I, Spain |
Optimizing Area on the
Generation of Specific Circuits in FPGAs for SIMD Applications |
regular
paper |
p33 |
J.
Varela, P. Bento, C. Leong, I. C. Teixeira, J. P. Teixeira, J. Nobre, J.
Rego, P.Lousã, P. Relvas, P. Rodrigues, A. Trindade |
LIP-Lisboa, Lisbon, Portugal;
Universidade Técnica de Lisboa, Instituto Superior Técnico, Lisbon, Portugal;
INESC-ID, Lisbon, Portugal; INOV, Lisbon, Portugal |
FPGA Based Architecture for the
Data Acquisition Electronics of the Clear-PEM System |
regular
paper |
p6 |
Wei Sheng CHONG and Masanori
HARIYAMA and Michitaka KAMEYAMA |
Tohoku University, Japan |
Novel Switch-Block Architecture
Using Reconfigurable Context Memory for Multi-Context FPGAs |
regular
paper |
p29 |
Remy
Eskinazi, Paulo Maciel, Manoel Eusebio de Lima, Paulo Sergio Nascimento, Abel
Guilhermino, Carlos Valderrama |
University of Pernambuco, Brasil |
AN ALGORITHM FOR HARDWARE TASKS
SCHEDULING OPTIMIZED IN TIME TO PARTIAL AND DYNAMIC RECONFIGURATION OF FPGAS |
regular
paper |
p7 |
Jürgen Foag, Roman Koch |
University of Luebeck, Germany |
Towards a Runtime Reconfigurable
Network-on-chip-based Network Processor |
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