<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">José Creissac Campos</style></author><author><style face="normal" font="default" size="100%">Michael Harrison</style></author></authors><secondary-authors><author><style face="normal" font="default" size="100%">P. Markopoulos</style></author><author><style face="normal" font="default" size="100%">P. Johnson</style></author></secondary-authors></contributors><titles><title><style face="normal" font="default" size="100%">The role of verification in interactive systems design</style></title><secondary-title><style face="normal" font="default" size="100%">Design, Specification and Verification of Interactive Systems - DSV-IS</style></secondary-title><tertiary-title><style face="normal" font="default" size="100%">Springer Computer Science</style></tertiary-title></titles><dates><year><style  face="normal" font="default" size="100%">1998</style></year><pub-dates><date><style  face="normal" font="default" size="100%">June</style></date></pub-dates></dates><urls><related-urls><url><style face="normal" font="default" size="100%">https://haslab.uminho.pt/sites/default/files/jccampos/files/camposh98.pdf</style></url></related-urls></urls><publisher><style face="normal" font="default" size="100%">Eurographics</style></publisher><pub-location><style face="normal" font="default" size="100%">Braga, Portugal</style></pub-location><pages><style face="normal" font="default" size="100%">155-170</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">&lt;p&gt;In this paper we argue that using verification in interactive systems development is more than just checking whether the specification of the system has all the required properties, and that changing the focus from a global specification into partial, property oriented, specifications can provide a number of advantages and  make verification actas an aid to decision making. We also present a compiler that allows for the verification of interactor specifications to be done in SMV, as well as a simple case study where verification is used to inform a design decision.&lt;/p&gt;
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